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CY7C1049V33
512K x 8 Static RAM
Features
* High speed -- tAA = 15 ns * Low active power -- 504 mW (max.) * Low CMOS standby power (Commercial L version) -- 1.8 mW (max.) * 2.0V Data Retention (660 W at 2.0V retention) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE features sion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O 7) is then written into the location specified on the address pins (A 0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049V33 is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground (revolutionary) pinout.
Functional Description
The CY7C1049V33 is a high-performance CMOS Static RAM organized as 524,288 words by 8 bits. Easy memory expan-
Logic Block Diagram
Pin Configuration
SOJ Top View
A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9
I/O0
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
I/O1
ROW DECODER
I/O2
SENSE AMPS 512K x 8 ARRAY
I/O3 I/O4 I/O5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC
CE WE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
A 11 A 12 A 13 A14 A15 A16 A17 A18
OE
1049V33-1
1049V33-2
Selection Guide
1049V33-12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Com'l/Ind'l Com'l L 12 150 8 0.5 1049V33-15 15 140 8 0.5 1049V33-17 17 130 8 0.5 1049V33-20 20 120 8 0.5 1049V33-25 25 110 8 0.5
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 June 2, 1999
CY7C1049V33
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V DC Input Voltage[1] ................................ -0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range Commercial Industrial Ambient Temperature[2] 0C to +70C -40C to +85C VCC 3.3V 0.3V
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND < V I < V CC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f=0 Com'l/Ind'l Com'l L Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -1 -1 7C1049V33-12 7C1049V33-15 7C1049V33-17 Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 150 30 2.2 -0.5 -1 -1 Max. Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 140 30 2.2 -0.5 -1 -1 Max. Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 130 30 Max. Unit V V V V A A mA mA
ISB2
8 0.5
8 0.5
8 0.5
mA mA
Shaded areas contain preliminary information. Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "Instant On" case temperature.
2
CY7C1049V33
Electrical Characteristics Over the Operating Range (continued)
7C1049V33-20 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs
[1]
7C1049V33-25 Min. 2.4 Max. Unit V 0.4 2.2 -0.5 -1 -1 VCC + 0.5 0.8 +1 +1 110 30 V V V A A mA mA
Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA
Min. 2.4
Max.
0.4 2.2 -0.5 VCC + 0.5 0.8 +1 +1 120 30
Input Load Current
GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. V CC, CE > VIH VIN > V IH or VIN < V IL, f = fMAX Max. V CC, CE > VCC - 0.3V, VIN > V CC - 0.3V, or V IN < 0.3V, f=0 Com'l/Ind'l Com'l L
-1 -1
ISB2
8 0.5
8 0.5
mA mA
Capacitance[3]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF
Note: 3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.3V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a)
1049V33-3
R1 317
THEVENIN EQUIVALENT 167 OUTPUT R2 351
ALL INPUT PULSES 3.3V 1.73V GND 3 ns 90% 10% 90% 10% 3 ns
(b)
1049V33-4
3
CY7C1049V33
Switching Characteristics[5] Over the Operating Range
7C1049V33-12 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE HIGH to High Z
[5, 6]
7C1049V33-15 Min. 15 Max.
7C1049V33-17 Min. 17 Max. Unit ns 17 3 17 8 0 8 3 8 0 17 17 13 13 0 0 13 9 0 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 ns
Description
Min. 12
Max.
12 3 12 6 0 6 3 6 0 12 12 10 10 0 0 10 7 0 3 6 15 12 12 0 0 12 8 0 3 0 3 0 3
15 15 7 7 7 15
CE LOW to Low Z[6]
[5, 6]
CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[6] [5, 6]
WRITE CYCLE[7, 8]
7
Shaded areas contain preliminary information. Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
4
CY7C1049V33
Switching Characteristics[5] Over the Operating Range (continued)
7C1049V33-20 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z
[5, 6]
7C1049V33-25 Min. 25 Max. Unit ns 25 5 25 10 0 10 5 10 0 25 25 15 15 0 0 15 10 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 ns
Description
Min. 20
Max.
20 3 20 8 0 8 3 8 0 20 20 13 13 0 0 13 9 0 3 8
CE LOW to Low Z[6] CE HIGH to High Z[5, 6] CE LOW to Power-Up CE HIGH to Power-Down
[7]
Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z
[5, 6]
Data Retention Characteristics Over the Operating Range (For L version only)
Parameter VDR ICCDR tCDR[3] tR[9] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC - 0.3V VIN > V CC - 0.3V or V IN < 0.3V Conditions[10] Min. 2.0 330 0 tRC Max Unit V A ns ns
Notes: 9. t r < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds. 10. No input may exceed VCC + 0.5V.
5
CY7C1049V33
Data Retention Waveform
DATA RETENTION MODE VCC CE
1049V33-5
3.0V tCDR
VDR > 2V
3.0V tR
Switching Waveforms
Read Cycle No. 1[11, 12]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1049V33-6
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS tRC CE
tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB 1049V33-7 ICC HIGH IMPEDANCE
Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW.
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CY7C1049V33
Switching Waveforms (continued)
Write Cycle No. 1(WE Controlled, OE HIGH During Write)[14, 15]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 16 tHZOE DATAIN VALID
1049V33-8
tHD
Write Cycle No. 2 (WE Controlled, OE LOW)[15]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 16 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
1049V33-9
Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 16. During this period the I/Os are in the output state and input signals should not be applied.
Truth Table
CE H L L L OE X L X H WE X H L H I/O 0 - I/O7 High Z Data Out Data In High Z Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
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CY7C1049V33
Ordering Information
Speed (ns) 12 15 17 20 Ordering Code CY7C1049V33-12VC CY7C1049V33L-12VC CY7C1049V33-15VC CY7C1049V33L-15VC CY7C1049V33-17VC CY7C1049V33L-17VC CY7C1049V33-20VC CY7C1049V33L-20VC CY7C1049V33-20VI 25 CY7C1049V33-25VC CY7C1049V33-25VI Document #: 38-00643-B Package Name V36 V36 V36 V36 V36 V36 V36 V36 V36 V36 v36 Package Type 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ Industrial Commercial Industrial Operating Range Commercial
Package Diagram
36-Lead (400-Mil) Molded SOJ V36
51-85090
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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